A network device, such as a switch or router, may include a network processor. The network processor often is employed for handling the transmission of data, such as cells or frames, from one or more connections into and out of the network device. The network device may store information in memory using one or more control structures (e.g., control blocks) corresponding to the connection from which data is transmitted into the network processor. The network processor may typically store 250,000 or more control structures in memory. Therefore, a large memory is needed to store the control structures. Due to the size limitations of the network processor, the large memory is generally external to the network processor.
One or more components of the network processor may modify information stored in the control structures. For example, every time the network processor receives a cell or frame from a connection, one or more components of the network processor may access the external memory to modify information stored in one or more control structures.
Due to limited memory bandwidth, external memory access may become a rate limiting step or bottleneck for the network processor. Because it is desirable to receive data in and/or transmit data from a network processor at speeds faster than an external memory access time, a need exists for methods and apparatus of providing high-speed scheduling of data for a network processor.